3Example Design Our example design is a serial adder. Since i'm not skilled enough in design with clock (except some silly flip flop i've found on the web, and similarly a register, where the design is pretty much the same) i have some. I've a design problem in VHDL with a serial adder. Any suggestion for such simple design? Ok here i have my first attempt for the design. But i'm not sure if this is the right way to perform this design, i would like to keep as much close i can to the diagram i posted. I'm not sure however how the whole entity for the adder should be designed i would attempt with something like entity adderSerial is generic(n: natural) port(x, y: in std_logic_vector(n - 1 downto 0) clk: in std_logic z: out std_logic_vector(n - 1 downto 0)) end entity adderSerial The internal architecture confuse me a lot since actually i don't know how to behave in the synchronization stuff.Īt high level i would say probably internally should be even a counter that probably keep track of when all the bits are being processed. Register and flip flop should be updated and shift for every clock cycle, the full adder is combinatorial so it is ok. I would start with a register (n bit) a full adder and than a flip flop as basic component. Since i'm not skilled enough in design with clock (except some silly flip flop i've found on the web, and similarly a register, where the design is pretty much the same) i have some problem in the design.
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